Design of a Digital Lock-In Amplifier Using Xilinx System Generator

Abstract

In this paper, a digital lock-in amplifier is designed using Xilinx System Generator. The designed digital lock-in amplifier is used to simulate values of the following nominal capacitances: 2.2 pF, 4.7 pF, 5.6 pF, 6.8 pF and 10 pF. The digital lock-in amplifier consists of an internal signal generator, two multipliers, 2 FIR low-pass filters and an ARCTAN block. The internal signal generator uses Direct Digital Synthesis to produce 50 kHz sine and cosine reference signals. The low-pass filters are designed using FIR Compiler blocks. The outputs of the low-pass filters are in-phase and quadrature components. CORDIC ATAN block converts in-phase and quadrature components into amplitude and phase values which are in proportional to the value of the measured capacitance. Analog noise and quantization error of analog-to-digital converter are added to obtain more realistic simulations. The digital lock-in amplifier in SIMULINK environment is compiled, and hardware description language bitstream is generated for Xilinx ZedBoard FPGA. The bitstream is downloaded into the FPGA and hardware-software cosimulation is performed. Relative errors are calculated for the nominal value and the measured value.