Simulation and Theoretical Analysis of a Digital Capacitance Measurement Circuit

Abstract

This paper presents theoretical analysis and simulation of a digital capacitance measurement circuit. The capacitance measurement circuit setup consists of a digital signal processing unit and a transimpedance amplifier. An unknown capacitance is excited by an input signal generated by a digital signal processing unit. Transimpedance amplifier converts the current flowing on the unknown capacitance into a voltage value. This modulated voltage is sampled by an analog-to-digital converter. The digital lock-in amplifier can be built on the digital signal processing unit, and it outputs a voltage value proportional to the unknown capacitance. The effects of the transimpedance amplifier’s analog noise and analog-to-digital converter’s quantization errors are examined. Total noise, sensitivity, resolution, signal-to-noise ratio, settling time, response time and relative measurement error are the simulated performance metrics of the measurement circuit. 4.7 pF and 15 pF are chosen as the values of the unknown capacitance. The simulations are run for 50 kHz and 100 kHz excitation frequencies.